Prashnikaप्रश्निका

Boolean Algebra - ISC Class 12 Computer Science Questions with Answers, Page 3

189 past-paper questions on Boolean Algebra from ISC Class 12 Computer Science papers (2026-2017), newest first, in full. Questions 41-60 are on this page, 20 to a page. Tap "Show answer" under a question to see its answer.

Practise these questions with filters
2025 · 1 mark · MCQOpen: Distributive law states that:

Choose the correct option.

Distributive law states that:
  • (a)$A + B \cdot C = (A + B) \cdot (A + C)$
  • (b)$A + (A \cdot B) = A$
  • (c)$A \cdot (B + C) = (A \cdot B) + (B \cdot C)$
  • (d)$A + B \cdot C = A \cdot B + A \cdot C$
Show answer

Answer

Official answer key

Correct option: (a)

Answer: (a) $A + B \cdot C = (A + B) \cdot (A + C)$ The Distributive Law has two dual forms: $A \cdot (B+C) = A \cdot B + A \cdot C$ (AND over OR) and $A + (B \cdot C) = (A+B) \cdot (A+C)$ (OR over AND). Option (a) is the second, correct form.
2025 · 1 mark · Assertion-reasonOpen: The truth table for the XOR gate shows that the output is HIGH only when an odd…

Study the Assertion and Reason and choose the correct option.

Assertion: The truth table for the XOR gate shows that the output is HIGH only when an odd number of inputs are HIGH.

Reason: The XOR gate performs addition modulo 2, thus producing a HIGH output when the number of HIGH inputs is odd.

  • (a)Both A and R are true, and R is the correct explanation of A.
  • (b)Both A and R are true, but R is not the correct explanation of A.
  • (c)A is true, but R is false.
  • (d)A is false, but R is true.
Show answer

Answer

AI

Correct option: a

Answer: (a) Both A and R are true, and R is the correct explanation of A. For a 2-input XOR gate the output is HIGH exactly when the inputs differ, i.e. exactly one input (an odd count) is HIGH, matching the assertion. This is because XOR performs addition modulo 2, which is HIGH precisely when the number of HIGH inputs is odd - exactly what the reason states, so R correctly explains A.
2025 · 1 mark · Assertion-reasonOpen: The expression is logically equivalent to Given below are two statements…

Study the Assertion and Reason and choose the correct option.

Assertion: The expression $\sim ( X \vee Y )$ is logically equivalent to $(\sim X \wedge \sim Y)$

Reason: The commutative property of logical operators states that the order of the operands does not change the result of a binary operation.

Given below are two statements marked, Assertion and Reason. Read the two statements carefully and choose the correct option.
  • (a)Both Assertion and Reason are true and Reason is the correct explanation for Assertion.
  • (b)Both Assertion and Reason are true but Reason is not the correct explanation for Assertion.
  • (c)Assertion is true and Reason is false.
  • (d)Both Assertion and Reason are false.
Show answer

Answer

AI

Correct option: (b)

Answer: (b) Both Assertion and Reason are true but Reason is not the correct explanation for Assertion. Assertion: $\sim(X \vee Y) = (\sim X \wedge \sim Y)$ is true, by De Morgan's law. Reason: the commutative property (order of operands does not change the result of a binary operation) is also a true statement, but it is unrelated to De Morgan's law and does not explain why the Assertion holds.
2025 · 1 mark · Assertion-reasonOpen: The Equivalence expression is .

Study the Assertion and Reason and choose the correct option.

Assertion: The Equivalence expression is $p \leftrightarrow q$.

Reason: An Equivalence Statement always gives the final result as Contingencies.

  • (a)Both A and R are true, and R is the correct explanation of A.
  • (b)Both A and R are true, but R is not the correct explanation of A.
  • (c)A is true, but R is false.
  • (d)A is false, but R is true.
Show answer

Answer

AI

Correct option: c

Answer: (c) A is true, but R is false. The biconditional/equivalence of p and q is written p <-> q, so A is true. R is false as a general claim: an equivalence statement is not always a contingency - for example p <-> p is a tautology (always true) and p <-> ~p is a contradiction (always false), so equivalence statements can also be tautologies or contradictions.
2025 · 1 mark · MCQOpen: The canonical expression for is:

Choose the correct option.

The canonical expression for $F(x, y, z) = \Sigma(1, 3, 6)$ is:
  • (a)$(x \cdot y \cdot z') + (x \cdot y' \cdot z') + (x' \cdot y' \cdot z)$
  • (b)$(x + y + z') \cdot (x + y' + z') \cdot (x' + y' + z)$
  • (c)$(x' + y' + z) \cdot (x' + y + z) \cdot (x + y + z')$
  • (d)$(x' \cdot y' \cdot z) + (x' \cdot y \cdot z) + (x \cdot y \cdot z')$
Show answer

Answer

AI

Correct option: (d)

Answer: (d) (x'.y'.z) + (x'.y.z) + (x.y.z') Σ(1,3,6) gives minterms m1 = x'y'z, m3 = x'yz, m6 = xyz', so the canonical SOP is (x'.y'.z) + (x'.y.z) + (x.y.z').
2025 · 1 mark · MCQOpen: According to the Principle of Duality, the Boolean equation will be equivalent…

Choose the correct option.

According to the Principle of Duality, the Boolean equation $(X' + Y \cdot 0) \cdot X = 0$ will be equivalent to:
  • (a)$(X + Y' \cdot 1) \cdot X' = 1$
  • (b)$(X \cdot Y' + 1) + X' = 1$
  • (c)$(X' \cdot Y + 1) + X = 1$
  • (d)$(X' \cdot Y + 0) + X = 0$
Show answer

Answer

AI

Correct option: (c)

Answer: (c) (X'.Y+1)+X=1 By the Principle of Duality, interchange + with ., . with +, and 0 with 1, keeping the same grouping: (X' + Y.0).X = 0 becomes (X'.Y + 1) + X = 1.
2025 · 3 marks · DerivationOpen: From the logic gate diagram given below, derive the Boolean expression for X(A…

Derive the following from the logic gate diagram.

From the logic gate diagram given below, derive the Boolean expression for X(A, B, C) and reduce it using Boolean laws.
Figure for this question
Show answer

Answer

Checked answer.
$X = (A + A \cdot B) \cdot (B + B \cdot C) \cdot (C + C \cdot A) = A \cdot B \cdot C$
  1. From the diagram: the first AND gate gives $A \cdot B$, which is ORed with $A$: $A + A \cdot B$
  2. The second AND gate gives $B \cdot C$, which is ORed with $B$: $B + B \cdot C$
  3. The third AND gate gives $C \cdot A$, which is ORed with $C$: $C + C \cdot A$
  4. The three OR outputs go into an AND gate: $X = (A + A \cdot B) \cdot (B + B \cdot C) \cdot (C + C \cdot A)$
  5. By the Absorption law ($P + P \cdot Q = P$): $A + A \cdot B = A$, $B + B \cdot C = B$, $C + C \cdot A = C$
  6. Therefore $X = A \cdot B \cdot C$
2025 · 1 mark · MCQOpen: The compliment of the Boolean expression

Choose the correct option.

The compliment of the Boolean expression $A' \cdot (B \cdot C' + B' \cdot C)$
  • (a)$A' \cdot (B + C + B' + C)$
  • (b)$A + (B + C') \cdot (B + C')$
  • (c)$A + (B' + C) \cdot (B + C')$
  • (d)$A' \cdot (B' + C' + B' \cdot C)$
Show answer

Answer

Official answer key

Correct option: (c)

Answer: (c) $A + (B' + C) \cdot (B + C')$ By De Morgan's law, $[A' \cdot (B \cdot C' + B' \cdot C)]' = A + (B \cdot C' + B' \cdot C)' = A + (B' + C) \cdot (B + C')$.
2025 · 1 mark · MCQOpen: According to the Principle of duality, the Boolean equation will be equivalent…

Choose the correct option.

According to the Principle of duality, the Boolean equation $(A' + B) \cdot (1 + B) = A' + B$ will be equivalent to:
  • (a)$(A + B') \cdot (0 + B) = A + B'$
  • (b)$(A' \cdot B) + (0 \cdot B) = A' \cdot B$
  • (c)$(A' \cdot B) + (0 \cdot B) = A' + B$
  • (d)$(A' + B) \cdot (0 + B) = A' + B$
Show answer

Answer

Official answer key

Correct option: (b)

Answer: (b) $(A' \cdot B) + (0 \cdot B) = A' \cdot B$ By the Principle of Duality, every $+$ is replaced by $\cdot$, every $\cdot$ by $+$, and every $1$ by $0$ (and vice versa), leaving the variables unchanged. Applying this to $(A'+B)\cdot(1+B)=A'+B$ gives $(A'\cdot B)+(0\cdot B)=A'\cdot B$.
2025 · 10 marks · Case basedOpen: A superhero is allowed access to a secure Avengers facility if he / she meets…

Answer the following using a truth table and a Karnaugh map.

A superhero is allowed access to a secure Avengers facility if he / she meets any of the following criteria: • The superhero has Avengers' membership and possesses a high-security clearance badge OR • The superhero does not have Avengers membership but holds a special permit issued by S.H.I.E.L.D. along with a high-security clearance badge OR • The superhero is not a recognised ally but holds a special permit issued by S.H.I.E.L.D. along with a high-security clearance badge The inputs are:
INPUTS
ASuperhero has Avengers membership.
SSuperhero holds a special permit issued by S.H.I.E.L.D.
CSuperhero possesses a high-security clearance badge
LSuperhero is a recognised ally
(In all the above cases, 1 indicates YES and 0 indicates NO) Output: X – Denotes allowed access [1 indicates YES and 0 indicates NO in all cases]
(i)[5.0]
Draw the truth table for the inputs and outputs given above. Write the POS expression for X (A, S, C, L).
(ii)(a)[2.5]
Reduce the above expression X (A, S, C, L) by using 4-variable Karnaugh map, showing the various groups (i.e., octal, quads and pairs).
(ii)(b)[2.5]
Draw the logic gate diagram using NOR gates only for the reduced expression. Assume that the variables and their complements are available as inputs.

Draw: logic gate diagram using NOR gates only for the reduced expression

Show answer

Answer

AI
3(i): X = A.C + A'.S.C + L'.S.C (access allowed when: has membership AND clearance; OR lacks membership but has a SHIELD permit AND clearance; OR is not a recognised ally but has a SHIELD permit AND clearance) Truth Table:
ASCLX
00000
00010
00100
00110
01000
01010
01101
01111
10000
10010
10101
10111
11000
11010
11101
11111
POS expression (product of maxterms where X=0, in order A,S,C,L): $X(A,S,C,L) = (A+S+C+L)(A+S+C+L')(A+S+C'+L)(A+S+C'+L')(A+S'+C+L)(A+S'+C+L')(A'+S+C+L)(A'+S+C+L')(A'+S'+C+L)(A'+S'+C+L')$ 3(ii): Reducing X(A,S,C,L) using a 4-variable K-map, grouping the zeros (0s) since the circuit is to be built with NOR gates only, which naturally realise a POS (Product of Sums) expression: - Octet (8 cells): all cells where C=0 -> gives the POS factor $C$ - Quad (4 cells): the cells where A=0 and S=0 -> gives the POS factor $(A+S)$ Reduced (minimal) POS expression: $X = (A+S) \cdot C$ With NOR gates only: a NOR gate gives $(A+S)'$, and a second NOR gate with inputs $(A+S)'$ and $C'$ gives $[(A+S)' + C']' = (A+S) \cdot C$ by De Morgan's law.
2025 · 1 mark · MCQOpen: The canonical expression of is:

Choose the correct option.

The canonical expression of $F( P, Q, R) = \pi (2, 5, 7)$ is:
  • (a)$(P + Q' + R) \cdot (P' + Q + R') \cdot (P' + Q' + R')$
  • (b)$(P \cdot Q' \cdot R) + (P' \cdot Q \cdot R') + (P' \cdot Q' \cdot R')$
  • (c)$(P' + Q + R') \cdot (P + Q' + R) \cdot (P + Q + R)$
  • (d)$(P' \cdot Q \cdot R') + (P \cdot Q' \cdot R) + (P \cdot Q \cdot R)$
Show answer

Answer

AI

Correct option: (a)

Answer: (a) $(P + Q' + R) \cdot (P' + Q + R') \cdot (P' + Q' + R')$ For $\pi(2,5,7)$: maxterm 2 (010) gives $(P+Q'+R)$, maxterm 5 (101) gives $(P'+Q+R')$, maxterm 7 (111) gives $(P'+Q'+R')$.
2025 · 5 marks · Case basedOpen: Reduce the Boolean function by using 4-variable Karnaugh map, showing the…

Reduce the following using a Karnaugh map.

$F(P, Q, R, S) = \Sigma (0,1,2,5,7,8,9,10,13,15)$
(a)[4.0]
Reduce the Boolean function $F(P, Q, R, S) = \Sigma (0,1,2,5,7,8,9,10,13,15)$ by using 4-variable Karnaugh map, showing the various groups (i.e., octal, quads and pairs).
(b)[1.0]
Draw the logic gate diagram using NAND gates only for the reduced expression. Assume that the variables and their complements are available as inputs.

Draw: logic gate diagram using NAND gates only for the reduced expression

Show answer

Answer (b)

AI
NAND-only (NAND-NAND) implementation of $F = QS + Q'R' + Q'S'$: one 2-input NAND gate for each product term and a 3-input NAND gate combining them, since $[(QS)' \cdot (Q'R')' \cdot (Q'S')']' = QS + Q'R' + Q'S'$ by De Morgan's law.
Diagram for this answer
2025 · 1 mark · MCQOpen: According to the Principle of Duality, the Boolean equation will be equivalent…

Choose the correct option.

According to the Principle of Duality, the Boolean equation $(1 + Y) \cdot (X + Y) = Y + X'$ will be equivalent to:
  • (a)$(1 + Y') \cdot (X' + Y') = Y' + X$
  • (b)$(0 \cdot Y) + (X \cdot Y) = Y \cdot X'$
  • (c)$(0 + Y) \cdot (X + Y) = Y + X'$
  • (d)$(1 \cdot Y) + (X \cdot Y) = Y \cdot X'$
Show answer

Answer

AI

Correct option: (b)

Answer: (b) $(0 \cdot Y) + (X \cdot Y) = Y \cdot X'$ By the Principle of Duality, every AND ($\cdot$) is replaced by OR ($+$), every OR by AND, and every 1 by 0 (0 by 1), while variables/complements stay unchanged. Applying this to $(1+Y) \cdot (X+Y) = Y+X'$ gives $(0 \cdot Y) + (X \cdot Y) = Y \cdot X'$.
2025 · 5 marks · Case basedOpen: Answer the following Boolean algebra questions: . Find its corresponding…

Answer the following questions.

Answer the following Boolean algebra questions:
(a)[3.0]
$f(a, b, c) = a.b' + a.c + b.c'$. Find its corresponding Cardinal and Canonical sum-of-product expression?
(b)[2.0]
If $a=1, b=0, c=1, d=0$, then write maxterm and minterm for $F(a, b, c, d)$ in canonical form?
Show answer

Answer (a)

AI
$f(a,b,c) = a.b' + a.c + b.c'$ Truth table:
abcf
0000
0010
0101
0110
1001
1011
1101
1111
Cardinal (sum-of-minterms) form: $f(a,b,c) = \Sigma(2,4,5,6,7)$ Canonical SOP: $f(a,b,c) = a'bc' + ab'c' + ab'c + abc' + abc$

Answer (b)

AI
$a=1, b=0, c=1, d=0$ gives the binary code 1010, i.e. index 10. Minterm (variable uncomplemented if its value is 1, complemented if 0): $m_{10} = a.b'.c.d'$ Maxterm (variable complemented if its value is 1, uncomplemented if 0): $M_{10} = a' + b + c' + d$
2025 · 5 marks · Truth tableOpen: A student from the Electronics department is asked to design a digital alarm…

Answer the following using a truth table.

A student from the Electronics department is asked to design a digital alarm for a smart home security system for the outside area. It comprises a sensor and a digital identification (ID) card with six-digit personal identification number (PIN). The alarm is supposed to buzz if wrongful entry is attempted, either by breaking the glass window or by entering the wrong PIN. Following statements are the criteria for the alarm to buzz: • The sensor detects the door opening without scanning a digital ID card. or • The sensor detects the door opening by breaking of the door lock. or • The sensor detects the wrong pin entry thrice of the digital ID card while opening the door. The inputs are:
InputsDescription
DDoor opening
BBreaking of door lock
SScanning security card
PEntering correct six-digit pin less than three times
(In all the above cases 1 indicates Yes and 0 indicates No). Output: A – Denotes the buzz of security alarm system (1 indicates yes and 0 indicates no) Draw the truth table for the inputs and outputs given above. Write the canonical POS expression for A(D, B, S, P).

No answer yet.

2025 · 10 marks · Case basedOpen: A shopping mall announces a special discount on all its products as a festival…

Answer the following using a truth table and a Karnaugh map.

A shopping mall announces a special discount on all its products as a festival offer only to those who satisfy any one of the following conditions. • If he/she is an employee of the mall and has a service of more than 10 years. OR • A regular customer of the mall whose age is less than 65 years and should not be an employee of the mall. OR • If he/she is a senior citizen but not a regular customer of the mall. The inputs are :
INPUTS
EEmployee of the mall
RRegular customer of the mall
SService of the employee is more than 10 years
CSenior citizen of 65 years or above
(In all the above cases, 1 indicates yes and 0 indicates no.) Output: X - Denotes eligible for discount [1 indicates YES and 0 indicates NO in all cases]
(i)[5.0]
Draw the truth table for the inputs and outputs given above and write the SOP expression for $X(E, R, S, C)$.
(ii)(a)[2.5]
Reduce the above expression $X(E, R, S, C)$ by using 4-variable Karnaugh map, showing the various groups (i.e. octal, quads and pairs).
(ii)(b)[2.5]
Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as inputs.

Draw: logic gate diagram for the reduced expression

Show answer

Answer

Official answer key
3(i): Truth table:
ERSCX
00000
00011
00100
00111
01001
01010
01101
01110
10000
10011
10101
10111
11000
11010
11101
11111
(E,R,S,C 1 = yes, 0 = no.) X = 1 when: (Condition 1) employee with service > 10 years, i.e. E.S; OR (Condition 2) regular customer, not employee, age below 65, i.e. E'.R.C'; OR (Condition 3) senior citizen (C) who is not a regular customer, i.e. C.R'. $X(E,R,S,C) = \Sigma(1,3,4,6,9,10,11,14,15)$ Canonical SOP: $X = E'R'S'C + E'R'SC + E'RS'C' + E'RSC' + ER'S'C + ER'SC' + ER'SC + ERSC' + ERSC$ 3(ii): 4-variable K-map for $X(E,R,S,C)=\Sigma(1,3,4,6,9,10,11,14,15)$ (rows in order E'R', E'R, ER, ER'; columns in order S'C', S'C, SC, SC' - Gray code order): Groups formed: Quad 1: cells (1,3,9,11) -> $R'C$ Quad 2: cells (10,11,14,15) -> $ES$ Pair: cells (4,6) -> $E'RC'$ Reduced SOP expression: $X(E,R,S,C) = R'C + ES + E'RC'$
2025 · 5 marks · Case basedOpen: Reduce the Boolean function by using 4-variable Karnaugh map, showing the…

Reduce the following using a Karnaugh map.

$F(X, Y, Z, W) = \pi(0, 1, 2, 3, 4, 6, 8, 9, 11, 12)$
(a)[4.0]
Reduce the Boolean function $F(X, Y, Z, W) = \pi(0, 1, 2, 3, 4, 6, 8, 9, 11, 12)$ by using 4-variable Karnaugh map, showing the various groups (i.e., octal, quads and pairs).
(b)[1.0]
Draw the logic gate diagram for the reduced expression. Assume that the variables and their complements are available as inputs.

Draw: logic gate diagram for the reduced expression

Show answer

Answer (b)

AI
Logic gate diagram for $F = (X+W) \cdot (Y+W') \cdot (Z+W)$: three 2-input OR gates feeding one 3-input AND gate.
Diagram for this answer
2025 · 5 marks · Case basedOpen: From the given logic diagram: Derive Boolean expression and draw the truth…

Answer the following from the logic diagram.

From the given logic diagram:
Figure for this question
(a)[4.0]
Derive Boolean expression and draw the truth table for the derived expression.
(b)[1.0]
If $A = 1$, $B = 0$ and $C = 1$ then find the value of $X$.
Show answer

Answer (a)

Official answer key
From the logic diagram: Gate 1 is a NAND gate with inputs A and B, giving output (1) = $(A.B)'$. Gate 2 is an AND gate with inputs B' and C, giving output (2) = $B'.C$. Gate 3 is an OR gate combining (1) and (2), giving output (3) = $(A.B)' + B'.C$. The final gate is a NOT gate acting on (3), giving output $X = [(A.B)' + B'.C]'$. Truth table:
ABC(A.B)'B'.C(A.B)'+B'.CX
0001010
0011110
0101010
0111010
1001010
1011110
1100001
1110001

Answer (b)

Official answer key
$X = [(A.B)'+B'.C]'$. For $A=1, B=0, C=1$: $A.B = 1.0 = 0 \Rightarrow (A.B)'=1$. $B'=1 \Rightarrow B'.C = 1.1 = 1$. $(A.B)'+B'.C = 1+1 = 1$. $X = 1' = 0$.

Final answer: 0

Questions on other pages on Boolean Algebra

Other Computer Science chapters