‹ Back to the paper
Answer the following for the given Boolean function.
Draw the logic gate diagram for the reduced expression using only NAND gates. Assume that the…
Draw the logic gate diagram for the reduced expression using only NAND gates. Assume that the variables and their complements are available as inputs.
Draw: Logic gate diagram of the reduced expression using only NAND gates
Show the case
Given the Boolean function $F(A, B, C, D) = \Sigma ( 0, 2, 3, 4, 5, 8, 10, 11, 12, 13 )$.
Answer
Answer
AINAND-only (NAND-NAND) implementation of $F = BC' + B'C + C'D'$: one 2-input NAND gate for each product term, and a 3-input NAND gate combining them. By De Morgan's law, $[(BC')' \cdot (B'C)' \cdot (C'D')']' = BC' + B'C + C'D'$.
From ISC 2019 Computer Science Paper 1, question 4(a)(ii).
Check your working with the Boolean algebra solver: the steps law by law, the K-map and the logic circuit for any expression.