Computer Hardware - ISC Class 12 Computer Science Questions with Answers, Page 2

Answer the following from the logic gate diagram.

Answer the following from the logic gate diagram.

Draw the following.

Draw: logic circuit to decode the binary numbers 0001, 0101, 0111, 1000, 1010, 1100, 1110, 1111 to their hexadecimal equivalents

Answer the following.

Answer the following.

Draw the following.

Draw: logic circuit to encode the hexadecimal numbers 1, 3, 5, 6, 9, A, C, E to their binary equivalents

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Binary equivalents: $1=0001,\ 3=0011,\ 5=0101,\ 6=0110,\ 9=1001,\ A=1010,\ C=1100,\ E=1110$. This is an 8-line to 4-line ENCODER: each hex digit has its own input line (I1, I3, I5, I6, I9, I10, I12, I14), active (=1) when that value is selected. Four OR gates combine these input lines to produce the 4-bit binary output B3 B2 B1 B0 (B3 = MSB): $B_3 = I_9+I_{10}+I_{12}+I_{14}$ $B_2 = I_5+I_6+I_{12}+I_{14}$ $B_1 = I_3+I_6+I_{10}+I_{14}$ $B_0 = I_1+I_3+I_5+I_9$

Choose the correct option.

• (a)AND
• (b)NOT
• (c)OR
• (d)XOR

Draw the following.

Draw: Logic gate diagram of a 2-input OR gate using NAND gates only, with the expression at each step

Must show: NAND gates only, expression at each step

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2-input OR gate using only NAND gates (three NAND gates): Step 1: NAND1 with both inputs tied to A -> output = (A.A)' = A' Step 2: NAND2 with both inputs tied to B -> output = (B.B)' = B' Step 3: NAND3 with inputs A' (from NAND1) and B' (from NAND2) -> output = (A'.B')' = A + B (De Morgan's law) So A OR B = (A NAND A) NAND (B NAND B)

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Decoder vs Multiplexer: A decoder is a combinational circuit that converts n input (address) lines into a maximum of 2^n unique, mutually exclusive output lines. A multiplexer selects one out of 2^n input data lines, based on n select lines, and routes it to a single output line. 3:8 Decoder (Octal decoder): It has 3 input lines (A2, A1, A0) with their complements available, an Enable input E, and 8 output lines D0 to D7, each generated by a 4-input AND gate: D0 = E.A2'.A1'.A0' D1 = E.A2'.A1'.A0 D2 = E.A2'.A1.A0' D3 = E.A2'.A1.A0 D4 = E.A2.A1'.A0' D5 = E.A2.A1'.A0 D6 = E.A2.A1.A0' D7 = E.A2.A1.A0 An 8:1 multiplexer can be derived from the 3:8 decoder: if each decoder output Di is ANDed with a data input Ii and all eight AND outputs are fed into one 8-input OR gate, the circuit selects and outputs the data input corresponding to the 3-bit address, which is exactly an 8:1 multiplexer.

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A half adder is a combinational logic circuit that adds two single binary digits A and B, producing two outputs: SUM ($A \oplus B$) and CARRY ($A \cdot B$); it does not take any carry-in from a previous stage. Using only NAND gates (5 NAND gates, verified logically): NAND1: inputs A, B -> $N_1=(AB)'$ NAND2: inputs A, $N_1$ -> $N_2=(A \cdot N_1)'$ NAND3: inputs B, $N_1$ -> $N_3=(B \cdot N_1)'$ NAND4: inputs $N_2$, $N_3$ -> SUM $=(N_2 \cdot N_3)' = A \oplus B$ NAND5: inputs $N_1$, $N_1$ (tied together, acting as an inverter) -> CARRY $=N_1'=AB$

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Half adder: adds two bits (A, B) and gives SUM and CARRY; it has no input for a carry from a previous stage. Full adder: adds three bits (A, B and the carry-in C) and gives SUM and CARRY; it can be cascaded to add multi-bit numbers. Full adder expressions: $SUM = A'B'C + A'BC' + AB'C' + ABC = A \oplus B \oplus C$ $CARRY = AB + BC + AC$

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Answer the following.

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Encoder: a combinational circuit that converts one of $2^n$ active input lines into an n-bit binary code (e.g. octal to binary encoder: 8 inputs, 3 outputs). Difference: an encoder has $2^n$ inputs and n outputs and converts a signal into a code, while a decoder does the reverse: it has n inputs and $2^n$ outputs and activates the one output line selected by the n-bit input code. 4:1 multiplexer: it has four data inputs $I_0, I_1, I_2, I_3$, two select lines $S_1, S_0$ and one output Y. $Y = S_1'S_0'I_0 + S_1'S_0I_1 + S_1S_0'I_2 + S_1S_0I_3$ Working: the select lines choose which input is passed to the output.

$S_1$	$S_0$	Y
0	0	$I_0$
0	1	$I_1$
1	0	$I_2$
1	1	$I_3$

Only the AND gate whose select combination matches is enabled, so the output Y equals the selected data input.

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A decoder is a combinational circuit that converts n coded/binary input lines into a maximum of $2^n$ unique output lines, with exactly one output activated (HIGH) for each unique combination of inputs - it decodes a binary code into one active line among many. Difference from a multiplexer: A multiplexer (MUX) works the other way round - it has $2^n$ data input lines, n select lines, and a SINGLE output; it selects and routes ONE of its many data inputs to that single output based on the select-line combination (many-to-one). 2-to-4 decoder: 2 inputs A, B; 4 outputs D0, D1, D2, D3; built from 2 NOT gates (for A' and B') and 4 two-input AND gates: $D0 = A'B'$, $D1 = A'B$, $D2 = AB'$, $D3 = AB$

Choose the correct option.

• (i)$A \cdot B$
• (ii)$A' + B'$
• (iii)$A + B'$
• (iv)$A + B$

Choose the correct option.

• (a)AND gate and OR gate
• (b)OR gate and NOT gate
• (c)NAND gate and NOT gate
• (d)AND gate and NOT gate

Choose the correct option.

• (a)Full Adder
• (b)Decoder
• (c)Half Adder
• (d)Multiplexer

Choose the correct option.

• (i)$A + B \cdot C'$
• (ii)$((A + B)' \cdot C)'$
• (iii)$((A + B) \cdot C)'$
• (iv)$(A + B) \cdot C$

Choose the correct option.

• (a)8
• (b)10
• (c)5
• (d)6

Choose the correct option.

• (i)$F = ((A + B)' \cdot C)' + (A + B)$
• (ii)$F = (A + B)' \cdot (C + A + B)$
• (iii)$F = ((A + B) \cdot C)' + (A + B)$
• (iv)$F = (AB + C)' + (A + B)$