Draw the logic circuit to decode the following binary number (0001, 0101, 0111, 1000, 1010, 1100…

The 4-bit binary inputs are labelled A, B, C, D (A = MSB ... D = LSB). Each input line feeds a buffer (true form) and a NOT gate (complemented form). Each given binary number is decoded by one 4-input AND gate, taking the true or complemented form of A, B, C, D as required so the gate outputs 1 only for that exact combination: 0001 -> A'.B'.C'.D -> output labelled 1 0101 -> A'.B.C'.D -> output labelled 5 0111 -> A'.B.C.D -> output labelled 7 1000 -> A.B'.C'.D' -> output labelled 8 1010 -> A.B'.C.D' -> output labelled A 1100 -> A.B.C'.D' -> output labelled C 1110 -> A.B.C.D' -> output labelled E 1111 -> A.B.C.D -> output labelled F Hexadecimal equivalents: 0001 = 1, 0101 = 5, 0111 = 7, 1000 = 8, 1010 = A, 1100 = C, 1110 = E, 1111 = F.

A 4-to-16 line decoder built from eight 4-input AND gates. Four input lines A, B, C, D each also feed a NOT gate to make A', B', C', D' available. Each AND gate is wired to the correct combination of true/complemented literals (as listed above) so its output is 1 only for its designated 4-bit code; the 8 AND-gate outputs are labelled with their hexadecimal equivalents 1, 5, 7, 8, A, C, E, F.